1. Field of the invention
The present invention relates to the field of metal-oxide-semiconductor (MOS), electrically programmable and electrically erasable read-only memories (EEPROMs) and to electrically programmable read-only memories (EPROMs) having floating gates.
2 Related application
This application relates to copending application Ser. No. 892,446, filed Aug. 4, 1986, and entitled LOW VOLTAGE EEPROM CELL; copending application Ser. No. 157,362, filed Feb. 17, 1988, entitled PROCESSOR CONTROLLED COMMAND PORT ARCHITECTURE FOR FLASH MEMORY; copending application Ser. No. 157,361, filed Feb. 17, 1988, entitled PROGRAM/ERASE SELECTION FOR FLASH MEMORY; copending application Ser. No. 144,567, filed Jan. 12, 1988, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH EPROM; copending application Ser. No 1444,569 filed Jan. 12, 1988, entitled LOAD LINE FOR FLASH EPROM; all assigned to the assignee of the present invention.
3. Prior art
Fabrication of electrically programmable read-only-memories (EPROMs) utilizing metal-oxide-semiconductor (MOS) technology is well-known in the prior art (see U.S. Pat. Nos. 3,660,819; 4,142,926; 4,114,255; and 4,412,310). These EPROMs employ memories cells utilizing floating gates which are generally formed from polysilicon members completely surrounded by an insulator. Electrical charges are transferred into the floating gate using a variety of techniques such as avalanche injection, channel injection, Fowler-Nordeheim tunnelling, channel hot electron injection, etc. A variety of phenomena have been used to remove charge from the floating gate, including exposing the memory to ultraviolet radiation. The floating gate is programmed when a charge is stored in the floating gate. The cell is in an unprogrammed, or erased, state when the floating gate is discharged. Because of complex and time consuming procedures required to erase EPROMs, these devices have been used primarily in applications requiring read-only-memories.
Electrically programmable and electrically erasable read-only-memories (EEPROMs) were developed to provide the capability of electrically erasing programmed memory cells (see U.S. Pat. Nos. 4,203,138 and 4,099,196). Commercially available EEPROMs have generally used a thin oxide region to transfer the charge into and from a floating gate. In a typical memory, a two transistor cell is used. For instance, U.S. Pat. No. 4,203,158 discloses the fabrication of such an EEPROM cell. Further, U.S. Pat. No. 4,266,283 discloses the arrangement of EEPROMs into an array wherein X and Y select lines provide for the selection, programming and reading of various EEPROM cells. These EEPROM cells do not lend themselves to being reduced in substrate are as do the EPROM cells. Various techniques have been implemented to reduce the size of the memory array by providing higher-density cells. One such technique is disclosed in U.S. Pat. No. 4,432,075.
More recently, a new category of electrically erasable EPROMs/EEPROMs has emerged and these devices are sometimes referred to as "Flash" EPROMs or EEPROMs. In these flash memories, the entire array is simultaneously erased, electrically. The cells themselves use only a single device per cell and such cells are described in the afore-mentioned copending application Ser. No. 892,446. Another relevant art is an article entitled "A 256-K Bit Flash E.sup.2 PROM Using Triple-Polysilicon Technology", Masuoka et al., IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 4, August, 1987. The present invention is directed towards the use of these cells.
An attempt to provide higher-density, low voltage EEPROMs cell is disclosed in the afore-mentioned copending Application, Ser. No. 892,446, and entitled "Low Voltage EEPROM Cell". In this copending application, a one-transistor memory cell which uses channel injection for charging the floating gate and tunnelling for discharging the gate is disclosed. A single 5 volt potential is used with a higher programming/erasing potential of approximately 11 to 15 volts being generated on-chip. However, the memory cell of the one-transistor design uses the same transistor and the same oxide separating the transistor elements from the floating gate to both program and erase the floating gate. Because of the one-transistor design, an overerase condition of a memory cell is more prevalent than in the two-transistor design. An overerased condition must be avoided in order to prevent the one-transistor memory cell from becoming a depletion like transistor in the read mode. During the read mode an overerased memory cell will disable a whole column of a memory array if the memory cells are structured as an array. The overerased problem is not typically a concern with the two-transistor design or the quasi-one-transistor EEPROM design, which is disclosed in a copending patent application Ser. No. 009,998, filed Feb. 2, 1987, which is also assigned to the assignee of the present invention. However, again, the twotransistor design will require much bigger cell area while the quasi-one-transistor EEPROM described in the Ser. No. 009,998 reference requires more processing steps.
Typically when flash memory cells are fabricated, these memory devices are tested to determine for failed cells. However, in performing this test, only those devices having cells which have failed or fail during the test are identified. Because the memory cells are subjected to voltages which are encountered under normal operation, the prior art test method does not subject the memory cells to additional stress.
A related application Ser. No. 039,086, filed Apr. 16, 1987 and entitled "Self-Limiting Erase Scheme For EEPROM" describes a biasing scheme which self limits the erasing sequence of the memory cell to prevent an overerase condition. However, this scheme does not detect failures or potential failures when a device is tested after fabrication.
It is appreciated that what is needed is a circuit and a method of stress testing a memory cell with added stress to determine any potential memory cell failures which are not typically discovered in prior art test modes.